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Hardware Security
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Real-time Intelligent System Design for Secured Digital Communication |
Develop FPGA prototypes as gateways of Tx and Rx of the CPS to run intensive and high throughput architectures of the crypto algorithms |
Dr. M. Asan Basiri, Assistant Professor IIITDM, Kurnool |
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Design and Implementation of a Secure Scan Test Architecture to Counter Scan-based Side-channel Attacks |
Development of a secure scan Design-for-Test (DfT) architecture for protecting cryptographic chips against scan-based side-channel attacks |
Dr. Satyadev Ahlawat, Assistant Professor IIT Jammu |
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Neuro-memristive PUF for Biometric Sensing Chip |
Develop a lightweight hardware-based biometric system using CMOS image sensor nodes integrated with low-power analog neuro-memristive circuits & a Physical Unclonable Function generator |
Dr. A.P. James, Professor IIT Jammu |
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A fault attack resistant crypto-accelerator for ultra-lightweight encryption protocols of GIFT family in RISC-V architecture |
Implement RISC-based cryptographic accelerator design of Gift family of cipher |
Dr. Bodhisatwa Mazumdar, Assistant Professor IIT Indore |